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    • 专利摘要:
    DDR PSRAM AND WRITING AND WRITING METHODS. A dual data rate pseudo-SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller over a common bus according to a clock, and receives a double data rate data from the controller over the common bus according to a strobe data signal from the controller. The address decoder decodes the first single data rate data to obtain an address from memory. The data receiver stores the double data rate data in the memory address.
    公开号:BR102012022452B1
    申请号:R102012022452-6
    申请日:2012-09-05
    公开日:2020-11-03
    发明作者:Chih-Hsin Lin；Tsung-Huang Chen；Bing-Shiun Wang；Jen-Pin Su
    申请人:Mediatek Inc；
    IPC主号:
    专利说明:

    CROSS REFERENCE TO RELATED ORDERS
    This request is partly a continuation of U.S. Order No. 13 / 311,352, filed on December 5, 2011, which claims the benefit of Provisional Order No. 61 / 531,187, filed on September 6, 2011. BACKGROUND OF THE INVENTION Field of the Invention
    The invention relates to a pseudo-SRAM (PSRAM) and, more particularly, to a controller and memory device of a dual data rate pseudo-PSRAM (DDR), and the protocol between them. Description of the Related Art
    In portable applications, such as portable / wireless devices, the use of low power memory is essential. A PSRAM device meets the requirements of low power consumption and high density. A PSRAM, like a conventional dynamic random access memory (DRAM), contains dynamic memory cells, but in terms of interface and packaging, it has the appearance of a static random access memory (SRAM).
    A PSRAM can operate in a burst mode. The burst mode improves the speed of data storage and retrieval. In burst mode, specific functions must occur in a predetermined sequence. These functions are generally performed in response to command signals provided by a PSRAM device controller. The timing of the control signals is determined according to a clock signal and is aligned to an edge (rise or fall) of the clock signal or occurs after a predetermined time after the edge (rise or fall) of the clock signal. Furthermore, in burst mode, the PSRAM device can operate in fixed and variable modes of waiting states, where the waiting state determines a minimum number of clock cycles that pass before valid data is present on a bus of data.
    In a dual data rate (DDR) SDRAM device, both the rising and falling edges of the clock signal are trigger points for read and write operations. Compared to a single data rate SDRAM (SDR) device, the DDR SDRAM device using the same clock frequency will double the data rate, and a differential clock scheme will be used to comply with the timing accuracy requirements. increased. BRIEF SUMMARY OF THE INVENTION
    A dual data rate pseudo-SRAM (DDR PSRAM) and methods for writing and reading data from it are provided. A modality of a DDR PSRAM is provided. The PSRAM DDR comprises a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller over a common bus according to a clock, and receives a double data rate data from the controller over the common bus according to a strobe data signal from the controller. The address decoder decodes the first single data rate data to obtain an address from memory. The data receiver stores the dual data rate data in the memory address.
    Furthermore, a modality of a data writing method for a DDR PSRAM is provided. A first single data rate data from a controller is obtained over a common bus according to a clock. The first single data rate data is decoded to obtain a memory address in the DDR PSRAM. Double data rate data from the controller is obtained over the common bus according to a data strobe signal from the controller. The double data rate data is stored in the memory address.
    Furthermore, another modality of a DDR PSRAM is provided. The DDR PSRAM comprises a data receiver, a memory, an address decoder, a data transmitter and a data strobe generating unit. The data receiver receives a single data rate first data from a controller over a common clock-based bus. The address decoder decodes the single data rate data to obtain an address from memory. The data transmitter obtains the data stored in the memory address and provides double data rate data to the controller through the common bus according to the data obtained. The data strobe generating unit provides a data strobe signal to the controller and toggles the data strobe signal in response to the double data rate data. The controller receives the double data rate data according to the data strobe signal.
    In addition, a modality of a method of reading data for a DDR PSRAM is provided. A first single data rate data from a controller is obtained over a common bus according to a clock. The first single data rate data is decoded to obtain a memory address in the DDR PSRAM. The data stored in the memory address is obtained. A double data rate data is provided to the controller via the common bus in response to a data strobe signal according to the data obtained. The controller receives the double data rate data according to the data strobe signal.
    A detailed description is given in the following modalities with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS
    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the associated drawings, in which: figure 1 shows an electronic device comprising a controller and a DDR PSRAM; figure 2 shows a waveform illustrating the signals between the controller 10 and the DDR PSRAM of figure 1; figure 3 shows an operating method for a low pin count DDR PSRAM (for example, the PSRAM of figure 1) according to an embodiment of the invention; figure 4 shows a waveform illustrating the signals of figure 1 according to the method of operation of figure 3; figure 5 shows a controller for a low pin count DDR PSRAM (for example, the PSRAM of figure 1) according to an embodiment of the invention; figure 6 shows a waveform illustrating the signals of the controller of figure 5 according to an embodiment of the invention, where the controller performs a synchronous write operation with 4 bursts for a low pin count DDR PSRAM (for example, the PSRAM of figure 1); figure 7 shows a waveform illustrating the signals from the controller of figure 5 according to an embodiment of the invention, where the controller performs a synchronous reading operation with 4 bursts for a low pin count DDR PSRAM (for example, the PSRAM of figure 1); figure 8 shows a low pin count DDR PSRAM according to an embodiment of the invention; figure 9 shows a waveform illustrating the DDR PSRAM signals of figure 8 according to an embodiment of the invention, in which a controller performs a synchronous write operation with 4 bursts for the low pin count DDR PSRAM; figure 10 shows a waveform illustrating the DDR PSRAM signals of figure 8 according to an embodiment of the invention, in which a controller performs a synchronous reading operation with 4 bursts for the low pin count DDR PSRAM; and figure 11 shows a dual data rate unit of a low pin count DDR PSRAM data transmitter according to an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
    The following description is the best contemplated way of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by a reference to the appended claims.
    Figure 1 shows an electronic device 100. The electronic device 100 comprises a controller 10 and a DDR PSRAM 20. Furthermore, the electronic device 100 further comprises a plurality of unidirectional transmission lines and a plurality of bidirectional transmission lines with a tri -state between controller 10 and DDR PSRAM 20. Lines 110 and 120 are unidirectional transmission lines for providing a pair of CLK and CLKn clock signals from controller 10 to DDR PSRAM 20. Line 130 is a unidirectional line for providing a CS chip selection signal from controller 10 to DDR PSRAM 20. Bus 140 comprises a plurality of unidirectional transmission lines for the provision of a CMD command signal from controller 10 for DDR PSRAM 20. Line 150 is a unidirectional line for providing a WAIT wait signal from DDR PSRAM 20 to controller 10, where the WATT wait signal is used o to notify controller 10 when valid data with double data rate is present on bus 130. Line 160 is a bidirectional transmission line for transferring a DQS data strobe signal between controller 10 and DDR PSRAM 20 The bus 170 is a common bus comprising a plurality of bidirectional transmission lines for the transfer of an AD address / data signal, wherein the AD address / data signal comprising address and data streams with different transfer rates. is multiplexed on bus 170. Compared to a conventional DDR PSRAM device, DDR PSRAM 20 is a low pin count memory (LPC) due to the sharing of address streams and data streams on bus 170.
    Figure 2 shows a waveform illustrating the signals between controller 10 and the DDR PSRAM in figure 1. With reference to figure 1 and figure 2 together, controller 10 disables the CS chip select signal to select the DDR PSRAM 20 at time tl, and then controller 10 provides a read command RD_CMD to DDR PSRAM 20 via the CMD command signal. At the same time, controller 10 also provides an ADDR address for DDR PSRAM 20 via the AD address / data signal. In one embodiment, the ADDR address can be divided into a high byte ADDR_H and a low byte ADDR_L, and controller 10 provides the high byte ADDR_H via the CMD command signal and provides the CLK clock signal via the address / data signal. AD. At time t2, controller 10 provides clock signals CLK and CLKn for DDR PSRAM 20, so that DDR PSRAM 20 can receive (alternatively it can refer to a search) the CMD command signal and the address signal / AD data according to the CLK and CLKn clock signals in a command state. For example, in figure 2, the DDR PSRAM 20 receives the command signal CMD and the address / data signal AD on a rising edge of the clock signal CLK at time t2. When the RD_CMD read command is accepted by the DDR PSRAM 20 from the CMD command signal, the DDR PSRAM 20 disables the WAIT wait signal at time t3, to notify the controller 10 to enter the wait state.
    When the RD_CMD read command and the ADDR address are accepted, the DDR PSRAM 20 performs a read operation to obtain the data from a DDR PSRAM 20 0 memory cell according to the ADDR address. Before transmitting the obtained data to controller 10, DDR PSRAM 20 activates the WAIT wait signal and disables the DQS data strobe signal in a CY1 clock cycle, which indicates that the obtained data is ready to be transmitted to the controller 10. In figure 2, the DDR PSRAM 2 0 is operating in a variable mode of the standby state, so the time period tRL is variable in clock cycles (reading latency) according to various specifications. At time t4, DDR PSRAM 20 starts to provide data obtained from DO to D7 to controller 10. Furthermore, DDR PSRAM 20 can alternate the DQS data strobe signal in response to DO to D7 data. Thus, controller 10 can receive data DO to D7 sequentially according to the rising and falling edges of the DQS data strobe signal. After data DO to D7 is received, controller 10 activates the command signal CMD at time t5 to end the read operation. Then, the WAIT wait signal and the DQS data strobe signal are both placed in a high impedance state on a CY2 clock cycle.
    In figure 2, the DQS data strobe signal is placed in a high impedance state until the standby state is terminated. Furthermore, for the data strobe signal DQS, a time period tLZ is referred to as a low impedance time from the rising edge of the CLK clock signal in the CY1 clock cycle. In general, the DQS data strobe signal is used to engage DO to D7 data, and a tracking circuit is used for tracking the DQS data strobe signal on a conventional controller. For example, when it is detected that the WAIT wait signal has been deactivated (or activated in another mode from a different design specification), the conventional controller needs to mask the imminence period of the DQS data strobe signal, so controlling the DQS data strobe signal by port. If the masked imminence period of the DQS data strobe signal is misinterpreted due to the variable time period tRL and the time period tLZ, it will be difficult to obtain valid data DO to D7 according to the data strobe signal DQS . For example, if the WAIT wait signal or the DQS data strobe signal derives from the CY1 clock cycle, a transient of the WAIT wait signal may be later than the tLZ time period, that is, the strobe signal of DQS data will be disabled earlier than the WAIT wait signal transient, thereby generating a time violation. Therefore, it is difficult to mask the imminence period of the DQS data strobe signal for the conventional controller, thus causing an invalid data hitch.
    Figure 3 shows an operating method for a low pin count DDR PSRAM (for example, PSRAM 20 in figure 1) according to an embodiment of the invention, and figure 4 shows a waveform illustrating the signals of the figure 1 according to the operation method of figure 3. With reference to figure 3 and figure 4 together, in step S302, the DDR PSRAM receives a single data rate data from a controller over a common bus coupled between the DDR PSRAM and the controller, where the single data rate data comprises an e n of the DDR PSRAM, as shown in a command state of figure 4. At the same time, the DDR PSRAM also receives a read command a from the controller via a command signal. In step S304, after the read command from the controller has been accepted, the DDR PSRAM provides a DQS data strobe signal and a WAIT wait signal for the controller and disables the DQS data strobe signal and the WAIT wait, as shown in a wait state in figure 4. Next, the DDR PSRAM provides a double data rate data comprising data stored at the DDR PSRAM address to the controller via the common bus (step S306), and the DDR PSRAM toggles the data strobe signal in response to the transmitted double data (step S308). If compared to figure 2, the data strobe signal of figure 4 is deactivated during the standby state, as shown on label 40, thus no time period tLZ in figure 2 exists. Therefore, the controller receives the double data rate data according to the DQS data strobe signal without masking the imminence period of the DQS data strobe signal. In other words, the controller can directly use the rising and falling edges of the DQS data strobe signal to engage the dual data rate data. Furthermore, the wait signal and data strobe signal are assigned to a high impedance until the read command from the controller is received by the DDR PSRAM, that is, the wait signal and data strobe signal are assigned to a high impedance in the control state. In addition, after data DO to D7 is received by the DDR PSRAM, controller 10 activates the CS chip select signal to end the read operation, and then the WAIT wait signal and the DQS data strobe signal are both placed in a state of high impedance.
    Figure 5 shows a controller 50 for a low pin count DDR PSRAM (for example, PSRAM 20 of figure 1) according to an embodiment of the invention. Controller 50 comprises a processor 510, a clock module 530, an address / data module 550, a data strobe module 570 and a standby module 590. Processor 510 controls clock module 530 for the provision of signals Differential CLK and CLKn for DDR PSRAM. The clock module 530 comprises a clock generator 532 and two output buffers 534 and 536, wherein clock generator 532 comprises a frequency divider 538. Clock generator 532 generates clock signals CLK1X and CLK2X according to a CLKin input clock, where the CLK2X clock signal is twice the frequency of the CLK1X clock signal. In one embodiment, the CLKin input clock is provided by an oscillator. Furthermore, the frequency divider 538 divides the CLK2X clock signal to generate the CLK1X clock signal. The CLK and CLKn clock signals are generated from the CLK1X clock signal, and have the same frequency as that of the CLK1X clock signal. Furthermore, the CLK and CLKn clock signals are provided for the DDR PSRAM via output buffers 536 and 534, respectively. Processor 510 controls the address / data module 550 for providing address flows to the DDR PSRAM in a horn phase, providing data flows to the DDR PSRAM in a data writing phase, and receiving data flows from from the DDR PSRAM in a data reading phase. The address / data module 550 comprises an output control unit 552, an output buffer 554, an input buffer 556, a single rate processing unit 558, a double rate processing unit 560, a selector 562, a data receiver 564 and a storage unit 566. Selector 562 is used to selectively provide any one of the single rate processing unit 558 and the double rate processing unit 560 for output buffer 554, according to a WDATA_PHASE_EN control signal. In this mode, selector 562 is a multiplexer (MUX). The processor 510 controls the data strobe module 570 to provide a data strobe signal to the DDR PSRAM in the data writing phase and to receive a data strobe signal from the DDR PSRAM in a data reading phase. The data strobe module 570 comprises an input buffer 572, an output buffer 574, a control unit per data strobe port 576, a data strobe generating unit 578 and an output control unit 580. The processor 510 controls the waiting module 590 to receive a waiting signal from the DDR PSRAM in the data reading phase. The standby module 590 comprises an input buffer 592, a synchronization unit 594 and a read control unit 596. The details of descriptions illustrating the operations of the address / data module 550, data strobe module 570 and the standby module 590 are described below.
    Figure 6 shows a waveform illustrating the signals from controller 50 of figure 5 according to an embodiment of the invention, in which controller 50 performs a synchronous write operation with 4 bursts for a low pin count DDR PSRAM ( for example, PSRAM 20 in figure 1). With reference to figure 5 and figure 6 together, for a period of time TP1, processor 510 provides a enable signal CMD_EN with a logic level HIGH for output control unit 552, in order to control the control unit output 552 to enable output buffer 554. At the same time, processor 510 also provides an ADDRO signal with ADDR address information for single rate processing unit 558. Next, single rate processing unit 558 obtains a single data rate data with ADDR address information according to the CLK1X clock signal, and provides the single data rate data for selector 562. Furthermore, processor 510 provides a WDATA_PHASE_EN control signal with a logic LOW level for selector 562, in order to control selector 562 to extract the single data rate data provided by the single rate processing unit 558, to the output buffer 554. Thus, an AD address / data signal with an ADDR address information is provided for the DDR PSRAM in a command phase. Meanwhile, a CMD command signal with a WR_CMD write command is sent to the DDR PSRAM via a command bus (for example, 140 in figure 1). Then, from a period of time TP2 to a period of time TP5, processor 510 provides the control signal WDATA_PHASE_EN with a logic level HIGH for output control units 552 and 580, in order to control the control units. output control 552 and 580 to enable output buffers 554 and 574. According to the fixed write latency (such as N cycles), processor 510 provides the control signal WDATA_PHASE_EN with a logic level HIGH when the cycle N CLK1X clock signal clock after sending the write command, in order to enter the data writing phase. Furthermore, processor 510 provides the control signal WDATA_PHASE_EN for selector 562, in order to provide an output from the dual rate processing unit 560 to output buffer 554. Processor 510 provides the signal WDATAO_L with a given D0 and the WDATAO_H signal with a D1 data for the double rate processing unit 560 during the TP3 time period, and the processor 510 provides the WDATAO_L signal with a D2 data and the WDTAO_H signal with a D3 data for the double rate processing unit 560 during the TP4 time period. The dual rate processing unit 560 provides a double data rate with data D0, D1, D2 and D3 for output buffer 554 through selector 562, according to the CLK2X clock signal. Thus, an AD address / data signal with data D0, Dl, D2 and D3 is provided for the DDR PSRAM in the data writing phase. In the modality, the double rate processing unit 560 alternatively provides the data of the WDATAO_L and WDATAO_H signals as the double data rate data according to the CLK2X clock signal. Therefore, the AD address / data signal with the data streams formed by the DO to D3 data can be transmitted to the DDR PSRAM in sequence. Furthermore, during time periods TP3 and TP4, processor 510 provides a DQSEN enable signal with a logic level HIGH for data strobe generation unit 578 in order to control data strobe generation unit 578 to provide a DQS data strobe signal to the DDR PSRAM via output buffer 574. Thus, the DDR PSRAM can receive the AD address / data signal according to the rising and falling edges of the DQS data strobe signal and then, the DDR PSRAM writes the data DO, Dl, D2 and D3 in memory cells of the same according to the address information ADDR.
    Figure 7 shows a waveform illustrating the signals from the controller 50 of figure 5 according to an embodiment of the invention, in which the controller 50 performs a synchronous reading operation with 4 bursts for a low pin count DDR PSRAM ( for example, PSRAM 20 in figure 1). With reference to figure 5 and figure 7 together, for a period of time TP6, processor 510 provides a enable signal CMD_EN with a logic level HIGH for output control unit 552, in order to control the control unit output 552 to enable output buffer 554. At the same time, processor 510 also provides an ADDRO signal with ADDR address information for single rate processing unit 558. Next, single rate processing unit 558 obtains a single data rate data with the ADDR address information according to the CLK1X clock signal and provides the single data rate data for selector 562. Furthermore, processor 510 provides a WDATA_PHASE_EN control signal with a logic level LOW for selector 562, in order to control selector 562 to extract the single data rate data provided by the single rate processing unit 558 to output buffer 554. Thus, an AD address / data signal with an inf ADDR address formatting is provided for the DDR PSRAM in a command phase. Meanwhile, a CMD command signal with an RD_CMD read command is sent to the DDR PSRAM via a command bus (for example, 14 0 in figure 1). As described in the operation method of figure 3, after the read command RD_CMD of the CMD command signal from the controller is accepted, the DDR PSRAM provides a DQS data strobe signal and a WAIT wait signal for the controller and disables the data strobe signal and the waiting signal in a waiting state. In the wait module 590, the input buffer 592 transmits the wait signal WAIT from the DDR PSRAM to the synchronization unit 594 for synchronization, and the synchronization unit 594 provides a synchronized wait signal to the reading control unit 596. Furthermore, processor 510 provides the enable signal RDATA_PHASE_EN with a logic level HIGH for 2 clock cycles after sending the RD_CMD read command, in order to enter a data reading phase. Furthermore, the reading control unit 596 provides a ready signal RDATA_PTR_GEN for storage unit 566. In a data reading phase, the data strobe control unit 576 is enabled by the enabling signal RDATA_PHASE_EN for control the DQS data strobe signal alternated by the DDR PSRAM, so as to obtain a signal controlled by the DQS_CG port and provide the signal controlled by the DQS_CG port to the reading receiver 564. The reading receiver 564 receives the address signal / AD data from the DDR PSRAM and stores the data of the AD address / data signal in first-in-first-out (FIFO) units of the storage unit 566, according to the DQS_CG port-controlled signal, where the address / data signal AD comprises data streams formed by data units DO, D1, D2 and D3 which are stored in the memory cells of the DDR PSRAM corresponding to the ADDR address information. For example, a first rising edge of the DQS_CG port controlled signal is used to engage the DO data at the FIFO FIFOR [0], a first falling edge of the DQS_CG port controlled signal is used to engage the D1 data at the FIFO FIFOF [ 0], a second rising edge of the DQS_CG port controlled signal is used to engage the D2 data on the FIFO FIFOR [1] and a second falling edge of the DQS_CG port controlled signal is used to engage the D3 data on the FIFO FIFOF [ 1]. In other embodiments, the storage unit 566 may comprise the recorder or other storage cells for storing the AD address / data signal data. Furthermore, the storage unit 566 provides the data units stored in FIFOR [1: 0] and FIFOF [1: 0] for processor 510 through the signals RDATA_IN_R and RDATA_IN_L, according to the ready signal RDATA_PTR_GEN. Thus, processor 510 obtains data D0, D1, D2 and D3 corresponding to the address information ADDR. After data D0, Dl, D2 and D3 are stored by processor 510, processor 510 disables the enable signal RDATA_PHASE_EN to end the data reading phase.
    Figure 8 shows a low pin count DDR PSRAM 60 according to an embodiment of the invention. The DDR PSRAM 60 comprises a control module 610, a hardware regulation unit 620, a clock module 630, a memory 640, a configuration register 650, an address decoder 660, an address / data module 710, a data strobe module 740 and a standby module 750. The control module 610 comprises a control unit 616, an input buffer 614 for receiving a CMD command signal from a controller (for example, 10 from the figure 1) and an input buffer for receiving a CS chip selection signal from the controller. The hardware regulation unit 620 provides two control signals HW1 and HW2 for the control unit 616 or the configuration register 650, where the control signals HW1 and HW2 are determined according to a hardware configuration of the DDR PSRAM 60 which is regulated by the pin belt or EFUSE. In the modality, the hardware regulation unit 620 provides the control signal HW1 to the control unit 616 to indicate that the DDR PSRAM 60 is operated in a single data rate mode or a double data rate mode, and the hardware control unit 620 provides control signal HW2 to control unit 616 to indicate whether to disable the DQS data strobe signal during a standby state, as described in figures 3 to 4. 0 630 clock module comprises a clock unit 636, an input buffer 632 for receiving a CLK clock signal from the controller and an input buffer 634 for receiving a CLKn clock signal from the controller. Memory 640 comprises a plurality of memory cells for storing data. The address / data module 710 comprises an output control unit 712, an output buffer 714, an input buffer 716, a data transmitter 72 0 and a data receiver 730. The control unit 616 can control the unit output control 712 to allow output buffer 714 to extract the AD address / data signal. In the address / data module 710, the data transmitter 720 provides data streams to the controller in a data readout phase. The data transmitter 720 comprises a selector 722, a single data rate unit 724 for single data rate data and a double data rate unit 726 for double data rate data. Selector 722 is used to selectively output the single data rate unit 724 and double data rate unit 726 to the controller via output buffer 714, according to a DDR_PSRAM_EN control signal provided by the configuration register 650, where the control signal DDR_PSRAM_EN is used to indicate that DDR PSRAM 60 is operated in a single data rate mode or a double data rate mode. In mode, the control signal DDR_PSRAM_EN is determined according to a command from the controller via the CS command signal or a hardware configuration of the hardware control unit 620. In the address / data module 710, the data receiver 730 receives address streams from the controller in a command phase and receives data streams from the controller in a data writing phase. The data receiver 73 0 comprises a selector 732, a single data rate unit 734 for single data rate data and a dual data rate unit 73 6 for double data rate data. Selector 732 is used to selectively output single data rate unit 734 and dual data rate unit 73 6 to memory 640, according to control signal DDR_PSRAM_EN from configuration register 650. On mode, selectors 722 and 732 are multiplexers (MUXs). The control unit 616 controls the data strobe module 740 to provide the DQS data strobe signal to the controller in the data read phase and to receive the DQS data strobe signal from the controller in the data write phase. Dice. The data strobe module 740 comprises an input buffer 742, an output buffer 744, a data strobe generating unit 746 and an output control unit 748. The control unit 616 can control the data control unit. output 74 8 to enable output buffer 744 for extracting the strobe signal from DQS data. The control unit 616 can control the data strobe generating unit 746 to toggle the DQS data strobe signal in response to a double data rate data from the AD address / data signal. Furthermore, the control unit 616 controls the standby module 750 to provide a standby signal for the DDR PSRAM in the data reading phase. The standby module 750 comprises an output buffer 752 and a standby processing unit 754. The details of descriptions illustrating the operations of the address / data module 710, the data strobe module 740 and the standby module 750 are described below.
    Figure 9 shows a waveform illustrating the DDR PSRAM 60 signals of figure 8 according to an embodiment of the invention, in which a controller (for example, 10 in figure 1) performs a synchronous write operation with 4 bursts for the low pin count DDR PSRAM 60. Referring to figure 8 and figure 9 together, first, on clock module 630, clock unit 636 receives clock signals CLK and CLKn from the controller for generation of a CLKin clock signal, where the CLKin clock signal has the same frequency as that of the CLK and CLKn clock signals. In one embodiment, the clock unit 636 can generate the CLKin clock signal only according to the CLK or CLKin clock signal, when the DDR PSRAM 60 is operated in a single data rate (SDR) mode, for example, the clock unit 636 can configure the CLK clock signal as the CLKin clock signal. Then, at time tl, the CS chip selection signal is deactivated by the controller, for notification to DDR PSRAM 60 regarding data access. Then, for a period of time TP1, the control unit 616 receives a CMD command signal with a WR_CMD write command from the controller. Simultaneously, the control unit 616 controls the configuration register 650, the address decoder 660 and the address / data module 710 to receive an AD address / data signal with an ADDR address information provided by the controller in one phase. command. At the data receiver 730, the single data rate unit 734 receives the AD address / data signal for obtaining the ADDR address information and provides the ADDR address information for the configuration register 650 and the address decoder 660. Then, the address decoder 660 decodes the ADDR address information to obtain a memory address 640 corresponding to the ADDR address information, and the configuration register 650 configures memory 640 according to the ADDR address information. In the mode, the command signal CMD and the address / data signal AD are engaged by the DDR PSRAM 60 in response to a lifting edge of the CLKin clock. According to a fixed write latency (such as N cycles), the controller can enter a data writing phase using the N clock cycle of the CLK clock signal, after sending the write command. Then, the address / data signal AD with data D0, D1, D2 and D3 written by the controller is received by the data receiver 73 0 in the writing data phase. If the control signal DDR_PSRAM_EN indicates that DDR PSRAM 6 0 is operated in a RECEIVED BROADCAST SIGNAL mode, for example, the control signal DDR_PSRAM_EN is at a low logic level, the single data rate unit 734 will receive the signal address / data AD in response to the CLKin clock to obtain data D0, Dl, D2 and D3, and then the control signal DDR_PSRAM_EN will control selector 732 for the passage of data D0, Dl, D2 and D3 to the memory 64 0 from the single data rate unit 734. Thus, data D0, D1, D2 and D3 are stored in memory address 640 corresponding to ADDR address information. Then, at time t2, the controller activates the chip select signal CS to complete the synchronous write operation. If the control signal DDR_PSRAM_EN indicates that DDR PSRAM 60 is operated in a dual data rate (DDR) mode, for example, the control signal DDR_PSRAM_EN will be set to a high logic level according to a command from the controller via the command signal CMD, the dual data rate unit 736 will receive the address / data signal AD in response to the data strobe signal DQS for obtaining data DO, D1, D2 and D3, where the strobe signal of DQS data from the controller is received by input buffer 742. In other words, data strobe module 74 0 is operated as an input mode. Furthermore, the dual data rate unit 73 6 can receive the AD address / data signal according to both the rising and falling edges of the DQS data strobe signal, when the DDR PSRAM 60 is operated in the double data rate. Then, the control signal DDR_PSRAM_EN controls selector 732 to pass data D0, Dl, D2 and D3 to memory 64 0 from the double data rate unit 736. Thus, data D0, Dl, D2 and D3 are stored in memory address 640 corresponding to ADDR address information.
    Figure 10 shows a waveform illustrating the DDR PSRAM 60 signals of figure 8 according to an embodiment of the invention, in which a controller (for example, 10 in figure 1) performs a synchronous reading operation with 4 bursts for the low pin count DDR PSRAM 60. Referring to figure 8 and figure 10 together, first, on clock module 630, clock unit 636 receives clock signals CLK and CLKn from the controller for generation of a CLKin clock signal, where the CLKin clock signal has the same frequency as that of the CLK and CLKn clock signals. Then, at time t3, the CS chip selection signal is deactivated by the controller, to notify the DDR PSRAM 60 of data access. Then, during the TP2 time period, the control unit 616 receives a CMD command signal with an RD_CMD read command from the controller. Simultaneously, the control unit 616 controls the configuration register 650, the address decoder 660 and the address / data module 710 to receive an AD address / data signal with the ADDR address information provided by the controller in a command phase. . At the data receiver 73 0, the single data rate unit 734 receives the AD data / address signal to obtain the ADDR address information and provides the ADDR address information for the configuration register 650 and the address decoder 660 Then, the address decoder 660 decodes the ADDR address information to obtain a memory address 640 corresponding to the ADDR address information, and the configuration register 650 configures memory 640 according to the ADDR address information. In the mode, the command signal CMD and the address / data signal AD are engaged by the DDR PSRAM 60 in response to a lifting edge of the CLKin clock. Furthermore, when the RD_CMD read command is accepted by the control unit 616 from the CMD command signal, the control unit 616 controls the wait processing unit 754 to disable the WAIT wait signal at time t4, to notify the controller to enter a standby state.
    In figure 10, the DDR PSRAM 60 is operated in a variable standby mode. Then, the control unit 616 controls the wait processing unit 754 to activate the WAIT wait signal at time t5, for notification of the controller to receive the data stored in memory address 640 corresponding to the ADDR address information in one phase. read data, that is, the double data rate data is ready to be transmitted to the controller. If the control signal DDR_PSRAM_EN indicates that DDR PSRAM 60 is operated in a single data rate (SDR) mode, for example, the control signal DDR_PSRAM_EN will be at a low logic level, the single data rate unit 724 of data transmitter 720 will obtain data D0, Dl, D2 and D3 stored in memory 640, and transmit the address / data signal AD with data D0, Dl, D2 and D3 to selector 722 in response to the CLKin clock, and, then, the control signal DDR_PSRAM_EN will control selector 722 to transmit data D0, Dl, D2 and D3 from the single data rate unit 724 to the controller. Thus, data D0, Dl, D2 and D3 stored in memory address 640 corresponding to address information ADDR are received by the controller according to the clock signals CLK and CLKn. Then, at time t6, the controller activates the chip select signal CS to complete the synchronous read operation.
    In figure 10, if the control signal DDR_PSRAM_EN indicates that DDR PSRAM 60 is operated in a dual data rate (DDR) mode, for example, the control signal DDR_PSRAM_EN will be set to a high logic level according to a command from the controller via the CMD command signal, the dual data rate unit 726 of the data transmitter 720 will obtain the DO, D1, D2 and D3 data stored in memory 640, and transmit the AD address / data signal with the data D0, Dl, D2 and D3 to selector 722 in response to the CLKin clock, and then the control signal DDR_PSRAM_EN will control selector 722 to transmit data D0, Dl, D2 and D3 from the data rate unit dual 726 to the controller, in response to the DQS data strobe signal provided by the data strobe module 74 0. In the dual data rate unit 726, the CLKin clock signal is used to provide data D0, Dl, D2 and D3 as the double data rate data. For example, the CLKin clock signal can control a multiplexer to alternatively provide the data stored in two buffers as the address / data signal AD with data D0, Dl, D2 and D3, as shown in figure 11. Furthermore, in one mode, the dual data rate unit 726 obtains data D0, Dl, D2 and D3 and transmits the address / data signal AD with data D0, Dl, D2 and D3 to selector 722, according to the operations similar to those of the storage unit 566 described in figure 5. Specifically, the dual data rate unit 726 alternatively provides the data from memory 64 0 as the double data rate data according to the strobe signal. Dice. Therefore, the controller can receive the AD address / data signal according to the rising and falling edges of the DQS data strobe signal, when DDR PSRAM 6 0 is operated in dual data rate mode, in order to obtain data D0, Dl, D2 and D3. Furthermore, the control unit 616 can selectively control the data strobe module 740 to disable the DQS data strobe signal during the standby state. For example, if the HW2 control signal indicates that the DQS data strobe signal needs to be disabled during the standby state, the DDR PSRAM 60 can provide the DQS data strobe signal and the WAIT wait signal for the controller and deactivate the data strobe signal and the wait signal in the waiting state after the read command RD_CMD of the CMD command signal from the controller is accepted, as shown by an arrow A. Otherwise, the DDR PSRAM 60 can provide only the WAIT wait signal to the controller and deactivate the wait signal in the waiting state after the read command RD_CMD of the CMD command signal from the controller is accepted. After the WAIT wait signal is activated, DDR PSRAM 60 provides the DQS data strobe signal to the controller, as shown in arrow B.
    Although the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the exposed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be evident to those skilled in the art). Therefore, the scope of the appended claims must be in accordance with the broadest interpretation to encompass all such modifications and similar arrangements.
    权利要求:
    Claims (27)
    [0001]
    1. Dual data rate pseudo-SRAM (DDR PSRAM), characterized by the fact that it comprises: a data receiver that receives a first single data rate data from a controller over a common bus according to a clock , and which receives double data rate data from the controller via the common bus according to a data strobe signal from the controller; a memory; and an address decoder, which decodes the first single data rate data to obtain a memory address, wherein the data receiver stores the double data rate data at the memory address.
    [0002]
    2. DDR PSRAM, according to claim 1, characterized by the fact that the data receiver receives the first single data rate data in a command phase and the double data rate data in a data writing phase.
    [0003]
    3. DDR PSRAM, according to claim 1, characterized by the fact that the clock and the data strobe signal are provided by the controller, and the data strobe signal is twice the clock frequency.
    [0004]
    4. DDR PSRAM according to claim 3, characterized by the fact that the double data rate data comprises a plurality of data units that are divided into a first group and a second group, and the data receiver receives the units of data from the first group in response to a rising edge of the data strobe signal and receives the data units of the second group in response to a falling edge of the data strobe signal.
    [0005]
    5. DDR PSRAM, according to claim 1, characterized by the fact that the data receiver comprises: a single data rate unit, which receives the first single data rate data in a command phase and which provides the first single data rate data for the address decoder; and a double data rate unit that receives the double data rate data in a data writing phase and which stores the double data rate data in memory.
    [0006]
    6. DDR PSRAM, according to claim 1, characterized by the fact that the data receiver receives a second single data rate from the controller or from the double data rate data through the common bus in a writing phase. data according to a control signal.
    [0007]
    7. DDR PSRAM according to claim 6, characterized by the fact that the data receiver comprises: a single data rate unit that receives the second single data rate data in the data writing phase and stores the second single data rate data in the memory address, when the control signal indicates that the DDR PSRAM is operated in a single data rate mode; and a double data rate unit, which receives the double data rate data in the data writing phase and which stores the double data rate data in the memory address, when the control signal indicates that the DDR PSRAM is operated in a dual data rate mode.
    [0008]
    8. DDR PSRAM according to claim 7, characterized by the fact that the control signal is determined according to a command from the controller or a hardware configuration of the DDR PSRAM.
    [0009]
    9. Method of writing data for a dual data rate pseudo-SRAM (DDR PSRAM), characterized by the fact that it comprises: obtaining a first single data rate data from a controller through a common data bus. according to a watch; decoding the first single data rate data to obtain a memory address in the DDR PSRAM; obtaining a double data rate data from the controller via the common bus according to a data strobe signal from the controller; and storing the double data rate data to the memory address.
    [0010]
    10. Data writing method according to claim 9, characterized by the fact that the first single data rate data is received in a command phase and the double data rate data is received in a data writing phase Dice.
    [0011]
    11. Data writing method according to claim 9, characterized by the fact that the double data rate data comprises a plurality of data units that are divided into a first group and a second group, and the obtaining step the double data rate data over the common bus according to the data strobe signal from the controller further comprises: obtaining the data units of the first group in response to a rising edge of the data strobe signal; and obtaining the data units of the second group in response to a falling edge of the data strobe signal.
    [0012]
    12. Data writing method, according to claim 9, characterized by the fact that it still comprises: obtaining a second single data rate data from the controller through the common bus in a data writing phase, when a control signal indicates that the DDR PSRAM is operated in a single data rate mode; and storing the second single data rate data at the memory address, where the double data rate data is received in the data writing phase, when the control signal indicates that the DDR PSRAM is operated in a double data rate.
    [0013]
    13. Dual data rate pseudo-SRAM (DDR PSRAM), characterized by the fact that it comprises: a data receiver that receives a first single data rate data from a controller over a common bus according to a watch; a memory; an address decoder, which decodes the single data rate data to obtain an address from memory; a data transmitter, which obtains the data stored in the memory address and which provides double data rate data for the controller through the common bus, according to the data obtained; and a data strobe generating unit, which provides a data strobe signal to the controller and which alternates the data strobe signal in response to the double data rate data, thereby enabling the controller to receive the data from double data rate according to the data strobe signal.
    [0014]
    14. DDR PSRAM, according to claim 13, characterized by the fact that the first single data rate data is received in a command phase and the double data rate data is transmitted in a data reading phase.
    [0015]
    15. DDR PSRAM according to claim 13, characterized in that the data stored in the memory address comprises a plurality of data units that are divided into a first group and a second group, and the data transmitter alternately provides the data units of the first and second groups as the double data rate data according to the data strobe signal, thereby enabling the controller to receive the data units of the first group in response to a signal rising edge data strobe and receive the data units of the second group in response to a falling edge of the data strobe signal.
    [0016]
    16. DDR PSRAM, according to claim 13, characterized by the fact that the data transmitter provides a second single data rate data or double data rate data to the controller via the common bus in a reading phase data according to a control signal.
    [0017]
    17. DDR PSRAM according to claim 16, characterized by the fact that the data transmitter comprises: a single data rate unit, which provides the second single data rate data for the controller in response to the according clock with the data obtained in the data reading phase, when the control signal indicates that the DDR PSRAM is operated in a single data rate mode; and a double data rate unit, which provides the double data rate data to the controller in response to the data strobe signal according to the data obtained in the data reading phase, when the control signal indicates that the DDR PSRAM is operated in a dual data rate data mode, in which the controller receives the second single data rate data according to the clock.
    [0018]
    18. DDR PSRAM according to claim 17, characterized in that the control signal is determined according to a command from the controller or a hardware configuration of the DDR PSRAM.
    [0019]
    19. DDR PSRAM, according to claim 13, characterized by the fact that it still comprises: a wait processing unit, which provides a wait signal for the controller, which disables the wait signal after a read command from the controller has been accepted, and that activates the wait signal when the double data rate data is ready to be transmitted to the controller, where the wait signal is assigned to a high impedance, until the read command from controller is accepted.
    [0020]
    20. DDR PSRAM, according to claim 19, characterized by the fact that the data strobe signal is assigned a high impedance until the controller read command is accepted, and the data strobe generating unit provides the data strobe signal to the controller after the read command from the controller is accepted or after the wait signal is activated according to a control signal.
    [0021]
    21. DDR PSRAM according to claim 20, characterized in that the control signal is determined according to a command from the controller or a hardware configuration of the DDR PSRAM.
    [0022]
    22. Method of reading data for a dual data rate pseudo-SRAM (DDR PSRAM), characterized by the fact that it comprises: obtaining a first single data rate data from a controller through a common bus according to a watch; decoding the first single data rate data to obtain a memory address in the DDR PSRAM; obtaining data stored in the memory address; and the provision of a double data rate data to the controller via the common bus in response to a data strobe signal according to the data obtained, wherein the controller receives the double data rate data according to the data strobe sign.
    [0023]
    23. Data reading method according to claim 22, characterized in that the first single data rate data is received in a command phase, and the double data rate data is transmitted in a data phase. reading data.
    [0024]
    24. Data reading method according to claim 22, characterized in that the data stored in the memory address comprises a plurality of data units that are divided into a first group and a second group, and the step of provision of the double data rate data to the controller via the common bus in response to the data strobe signal according to the data obtained further comprises: the provision of the data units of the first group in response to a rising edge of the signal data strobe as the double data rate data; and the provision of the data units of the second group in response to a falling edge of the data strobe signal as the double data rate data.
    [0025]
    25. Method of reading data, according to claim 22, characterized by the fact that it still comprises: the provision of a second single data rate data for the controller in response to the clock through the common bus according to the data obtained in a data reading phase, when a control signal indicates that the DDR PSRAM is operated in a single data rate mode; and the provision of double data rate data to the controller in response to the data strobe signal according to the data obtained in the data reading phase, when the control signal indicates that the DDR PSRAM is operated in a double data rate, in which the controller receives the second single data rate data according to the clock.
    [0026]
    26. Method of reading data, according to claim 22, characterized by the fact that it still comprises: the provision of a waiting signal for the controller; disabling the wait signal after a read command from the controller has been accepted; and activating the wait signal when the double data rate data is ready to be transmitted to the controller, where the wait signal is assigned to a high impedance until the controller read command is accepted.
    [0027]
    27. Data reading method, according to claim 26, characterized by the fact that it still comprises: the assignment of the data strobe signal to a high impedance, until the controller read command is accepted; and deactivating the data strobe signal after the read command from the controller is accepted or after the wait signal is activated according to a control signal.
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    同族专利:
    公开号 | 公开日
    US8705313B2|2014-04-22|
    CN102981776B|2015-06-10|
    US20140043925A1|2014-02-13|
    US8649210B2|2014-02-11|
    TW201312565A|2013-03-16|
    TWI474320B|2015-02-21|
    BR102012022452A2|2014-10-29|
    US20130058175A1|2013-03-07|
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    法律状态:
    2014-10-29| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    2018-12-11| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-11-19| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-05-05| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-11-03| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 05/09/2012, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US201161531187P| true| 2011-09-06|2011-09-06|
    US61/531,187|2011-09-06|
    US13/311,352|US8593902B2|2011-09-06|2011-12-05|Controller and access method for DDR PSRAM and operating method thereof|
    US13/311,352|2011-12-05|
    US13/403,689|2012-02-23|
    US13/403,689|US8649210B2|2011-09-06|2012-02-23|DDR PSRAM and data writing and reading methods thereof|
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